Processing parameters for heating of nano-scaled structures may be based on the material of the structures. For example, the formation of Si and Ge transistors (or III-V) on the same wafer poses a problem of the dopant anneal which requires very different temperatures for the Si junctions and Ge-junctions. Applying the higher temperature required for (strained) Si will negatively influence the Ge-junctions (and strain). Staying at the lower temperature required for Ge leads to poor activation for Si-based junctions. It is challenging, therefore, to utilize CMOS processes for substrates that include both Si and Ge devices.